The present invention relates generally to high voltage components and more specifically to high voltage components with low series resistance.
A problem with several high voltage component devices such as a doubly diffused MOS device (DMOS) is the large series resistance associated with the lightly doped region, for example the drain. Since the drain must support the high voltage, its doping is very light. This increases the resistance of the drain specifically from the channel to the drain contact. One method of the prior art which uses large area components to reduce the series resistance to acceptable values.
Although DMOS's is used as an example, other three layer devices which include two PN junctions also are generally formed in lightly doped background material and, thus, the series resistance of the lightly doped region is increased in order to support the high voltage. This applies to bipolar devices, MOS devices and four layer (SCR) devices.
Thus, it is an object of the present invention to provide a method which allows smaller area components to achieve a given resistance at a given breakdown voltage.
Another object of the present invention is to provide such components which both reduce the cost of the components and improve their performance.
Yet another object of the present invention is to produce such components with reduced current leakage and capacitance which are proportional to component area.
These and other objects of the invention are attained by forming an increased impurity concentration region between the lowest impurity concentration region and the second lowest impurity concentration region having the same conductivity type as the lowest impurity concentration region and having a doping profile such that this increased impurity concentration region is depleted under reverse biasing before critical field is reached therein. Thus, the increased impurity concentration region offers a lower series resistance while not affecting the breakdown characteristics of the high voltage PN junction. The increased impurity concentration region extends equally distant vertically and laterally from the second lowest impurity concentration region. The impurity concentration profile of the increased impurity concentration region is such that critical field is reached substantially simultaneously in the lowest impurity concentration region and the increased impurity concentration region. The increased impurity concentration region may be formed at the body-drain junction of an insulated gate field effect transistor or base collector junction of a bipolar transistor. In a four layer device, the increased impurity concentration region would be formed around the first and third layer portion of a four layer device. A method of forming the increased impurity concentration region would include forming the second lowest impurity concent ration region and the increased impurity concentration region through the same mask to assure vertical and lateral self-alignment. Other methods to form the equal lateral and vertical spread may also be used.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.